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December 3, 2010

ASIC Dv/Ds Engineer

ASIC Dv/Ds Engineer 

 Implementation (RTL2GDSII) of large ASIC/ASSP designs in 65 and 40 nm technologies and ensure LSI's rigorous criteria for achieving right-first time silicon.

Position involves floorplanning/partitioning, placement, physical optimization, clock insertion, post route optimization, static timing analysis, DRC/LVS and power estimation/analysis. Candidate will interact with IP and methodology organizations to clearly understand the implementation requirements.

Academic Credentials:
Bachelors/Masters Degree in Engineering specializing in Electronics & Communication / Telecommunication Engineering / Electrical Engineering only

A fresher from premier education institute (preferably - IIT's, NIT, and IISC) with exceptional academic credentials. A consistent academic record is a must.

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